1. Field of the Invention
The present invention relates to semiconductor devices and methods for their fabrication. Specifically, the present invention relates to surface P-channel transistors, including hardened gate oxides, possessing enhanced performance and reliability characteristics.
2. State of the Art
Higher performance, enhanced reliability, and greater packaging density of integrated circuits are constant goals of the semiconductor industry. However, as components become smaller and smaller to meet these goals, it becomes increasingly difficult to produce semiconductor devices capable of reliable, long-term operation, particularly in light of the operational stresses each component of a state of the art semiconductor device must endure. For example, as state of the art surface P-channel transistors decrease in size, the size and thickness of the gate oxides included in these transistors must also decrease, but as gate oxides shrink, they become more permeable to dopants included in overlying polysilicon electrodes, less resistant to hot electron degradation, and more susceptible to breakdown at voltages below normal operating parameters.
To combat such problems, various processes for hardening gate oxides have become essential to the fabrication of state of the art semiconductor devices, and several hardening processes are well-known in the art. For example, both furnace-based nitrogen processing and remote plasma-based nitrogen hardening (“RPN”) may be used to harden gate oxides. Relative to nonhardened devices, gate oxides hardened by known methods are generally less permeable to dopants included in polysilicon electrodes, more resistant to hot electron degradation, and less susceptible to breakdown at voltages below normal operating voltages. However, known processes for hardening gate oxides also have drawbacks. For example, after being subjected to such processes, gate oxides often contain a significant amount of unbound, or interstitial, nitrogen, which is mobile and may diffuse out of the gate oxide, reducing the effectiveness of the hardening procedure and contaminating the overlying polysilicon electrode. Further, in order to prevent diffusion of dopants from the polysilicon electrode and into and through the gate oxide, known hardening processes often provide a high concentration of nitrogen at the interface of the gate oxide and the underlying semiconductor substrate. However, as is known, excessive nitrogen at the gate oxide/substrate interface significantly degrades transistor performance.
In terms of device performance and reliability, it has been found to be advantageous to fabricate a gate oxide having a large nitrogen concentration (about 2.5% or greater nitrogen by atomic weight) at the interface of the gate oxide and the overlying polysilicon electrode while having a small nitrogen concentration (about 0.5% nitrogen by atomic weight) at the gate oxide/substrate interface. The large nitrogen concentration at the polysilicon electrode/gate oxide interface effectively prevents diffusion of dopants from the polysilicon electrode and into and through the gate oxide, while the small nitrogen concentration at the gate oxide/substrate interface confers resistance to hot electron degradation without substantially effecting device performance. Yet known processing techniques do not reliably provide surface P-channel transistors including a gate oxide having a large nitrogen concentration at the polysilicon electrode/gate oxide interface and a small nitrogen concentration at the gate oxide/substrate interface.
At least one method has been developed in an attempt to provide a transistor including a gate oxide having similar characteristics. U.S. Pat. No. 6,017,808 to Wang et al. (hereinafter “the '808 Patent”) describes a method for hardening a gate oxide designed to provide a transistor wherein a large peak of nitrogen exists within the polysilicon and oxide layers at the interface of the gate oxide and the overlying polysilicon electrode, while a relatively smaller nitrogen peak occurs within the oxide layer and the underlying semiconductor substrate at the interface of the gate oxide and the underlying semiconductor substrate. To achieve this structure, the method of the '808 Patent requires implanting nitrogen through the polysilicon layer and into the gate oxide layer followed by an anneal step. After the implantation and annealing steps, a first nitrogen peak occurs entirely within the polysilicon layer, a second nitrogen peak occurs within the polysilicon layer and the gate oxide at the polysilicon/gate oxide interface, and a third nitrogen peak occurs within the gate oxide layer and underlying substrate at the gate oxide/substrate interface. However, the first nitrogen peak located entirely within the polysilicon layer is problematic because it retards diffusion of subsequently implanted dopants, such as boron, within the polysilicon layer. Therefore, the method of the '808 Patent requires removal of only the portion of the polysilicon layer including the first nitrogen peak without removing the portion of the polysilicon layer including the second nitrogen peak. Once the portion of the polysilicon layer including the first nitrogen peak is removed, an additional, nitrogen-free polysilicon layer may be optionally formed over the remaining portion of the nitrogen implanted polysilicon layer.
As will be readily appreciated, achieving the structure disclosed in the '808 Patent using the methods described therein is at best problematic, particularly in light of the continually decreasing thicknesses of polysilicon electrodes included in state of the art semiconductor devices. One of the most problematic aspects of the method described in the '808 Patent is the need to remove only the portion of the nitrogen implanted polysilicon layer including the first nitrogen peak. The reference teaches that this task may be accomplished using known wet etch, dry etch, or chemical mechanical polishing processes. However, the polysilicon layers used for polysilicon electrodes in state of the art transistors are exceedingly thin. The polysilicon electrodes of some state of the art devices may be as thin as seven or fewer molecular monolayers, and known etching and polishing processes are difficult to control with sufficient precision to remove only predetermined portions of material layers of such minute thicknesses. Moreover, in this context, the polysilicon layer will include varying concentrations of nitrogen at any given depth, and as the nitrogen concentration varies, the etch rate will also vary, making precise control of the etching process even more difficult. Thus, removing only the portion of the polysilicon layer including the first nitrogen peak is extremely difficult, and known removal processes will most likely result in removal of too much or too little polysilicon material, resulting in transistors exhibiting impaired performance or reduced reliability.
It would, therefore, be desirable to provide a method for fabricating a surface P-channel transistor which provides a surface P-channel transistor including a hardened gate oxide characterized by a large nitrogen concentration at the polysilicon/gate oxide interface and a small nitrogen concentration at the gate oxide/substrate interface, and which can be accomplished without the need to partially remove the polysilicon layer overlying the gate oxide. Ideally, such a method could be easily incorporated into current fabrication processes and would reliably produce state of the art surface P-channel transistors exhibiting enhanced performance and reliability.